1. Technical Field
The present invention relates to a test apparatus and an electronic device. In particular, the present invention relates to an electronic device provided with an interface circuit that operates at high speed, and to a test apparatus that tests this electronic device.
2. Related Art
One test for a device such as a semiconductor circuit involves using a test signal having a frequency corresponding to the operational speed of the electronic device. In this case, the test apparatus for the electronic device (i) inputs, to the electronic device, a test pattern having a frequency corresponding to the operational speed of the electronic device, (ii) detects a logic value pattern of an output signal from the electronic device with a speed according to the frequency of this output signal, and (iii) compares this logic value pattern to an expected value pattern.
The test apparatus performing such a test may be provided with a pattern generator, a timing generator, a waveform shaper, a driver, a comparator, and a logical comparator, as shown in, for example, Japanese Patent Application Publication No. 2001-222897. The pattern generator generates a logic value pattern for the test pattern. The timing generator generates timing information of the logic value pattern. The waveform shaper and the driver generate the test signal to be input to the electronic device, based on the logic value pattern and the timing information.
The timing generator generates a timing signal that determines the bit rate of the test pattern, for example. The waveform shaper generates a test pattern in which the logic value transitions at the determined bit rate, based on the logic value pattern generated by the pattern generator. The driver outputs a voltage according to the logic value of the test pattern generated by the waveform shaper. An algorithm pattern generator (ALPG) may be used as the pattern generator to generate a test pattern having the desired logic value pattern.
An interface circuit of the electronic device receives the test signal from the test apparatus. The interface circuit inputs the test signal to an internal circuit of the electronic device, and the output signal of the internal circuit is supplied to the test apparatus.
The comparator of the test apparatus detects the logic value pattern of the output signal received from the interface circuit. The logical comparator detects whether the logic value pattern detected by the comparator matches a prescribed expected value pattern. In this way, the test apparatus can determine whether the interface circuit and the internal circuit of the electronic device are operating correctly.
In recent years, electronic devices have come to operate at much higher speeds. When testing high-speed electronic devices at the actual operation speed, a high-speed pattern generator is often used. For example, when testing an electronic device with an actual operation speed in the GHz range, a pattern generator that also operates in the GHz range is used. However, it is difficult for the pattern generator used in conventional test apparatuses, such as the algorithm pattern generator, to operate at a high frequency in the GHz range.
A technique is considered that involves providing a plurality of pattern generators and multiplexing the output of the pattern generators to generate a high-frequency test pattern. With this technique, however, the circuit size of the test apparatus becomes undesirably large.